In modern processor systems, peripheral units include a variety of input/output terminals and mass storage devices operating under the control of peripheral device controllers such as disk or tape controllers. Many peripheral units are semi-autonomous and require the attention of the system's central processor only for a relatively small period of the total processing time available to the system. Typically, a peripheral unit will act on command from the central processor or in response to external stimuli. In either case, the peripheral unit usually performs some autonomous tasks and signals the processor when further attention by the processor is needed. This signaling is commonly done with an interrupt request to the processor. The processor will acknowledge concurrent interrupt requests from different peripheral units in accordance with a predetermined priority scheme assigned on the basis of the type and activity of the requesting device.
Modern processor systems generally consist of integrated circuits mounted on circuit boards. In some arrangements, an entire processor may be mounted on a single board which, in turn, is plugged into a so-called backplane. The computer's peripheral units are connected to peripheral interface circuit boards which are also plugged into the same backplane board as the processor. Interconnecting buses including address and data buses for transferring information between circuit boards, and an interrupt bus used to communicate interrupt request and acknowledge signals between the interface circuit boards and the processor, are formed on the backplane. The interrupt bus includes a communication path to transmit interrupt request signals from peripheral unit interface boards to the processor and a path to transmit acknowledge signals from the processor to the interface boards.
As the number of peripheral units of a processor increases, the processor's peripheral communication overhead increases as well. To alleviate this problem, some prior art arrangements use secondary support processors, connected to the interrupt bus of the central processor, which handle a part of the peripheral unit communications. The central processor, the secondary processors and all of the system's peripheral interface circuits are interconnected by an address/data bus which allows communication among the various units. The secondary processors and certain of the system's peripheral interface circuits are connected to the central processor's interrupt bus, and are capable of interrupting the central processor; however, certain other peripheral units have no connection to the central processor's interrupt bus. Interrupt communications with these other units are controlled from the secondary processors by "polling", that is, reading certain status bits within the peripheral units via the address/data bus. While this scheme relieves the primary processor of some of the tasks associated with serving peripheral equipment, it does not allow the peripheral units served by secondary processors to initiate interrupts and no provision exists for conveniently allowing distinct levels of interrupts for different peripheral units connected to the secondary processors.